The present invention relates to a universal platform suitable for software defined radio and capable of handling multiple radio standards.
After the first technical paper was presented in 1992, software defined radio (SDR) has been receiving much attention among researchers working on wireless communications (refer to J. Mitola III, D. Chester, S. Haruyama, T. Turletti, and W. Tuttlebee, xe2x80x9cGlobaliazation of Software Radio,xe2x80x9d IEEE Communications Magazine, vol.37, no.2, pp.82-83, February 1999, and R. Kohno, xe2x80x9cPrespective of Software Radio: Spatial and Temporal Communication Theory Using Adaptive Array Antenna for Mobile Radio Communicationsxe2x80x9d, Proceeings on Microwave Workshops and Exhibition (MWE ""97), December 1997). There is a conceptual reason and a technical reason behind this popularity (refer to J. Mitola III, xe2x80x9cTechnical Challenges in the Globalization of Software Radio,xe2x80x9d IEEE Communications Magazine, vol.37, no.2, pp.84-89, February 1999).
The conceptual reason is that various wireless standards have been established through generations of wireless communication systems. Even in the same generation, several standards have been created in different regions.
As an example, the standardization efforts surrounding IMT2000/UMTS have tried to resolve the dispute over what the third generation standard should entail. Despite all of this, it still seems as if three slightly varying code division multiple access (CDMA) standards will be introduced in the near future.
For wireless local area networks (LAN), not only IEEE standards, but also de facto standards such as Bluetooth have gained wide acceptance among companies all over the world. Thus, a multiband multimode radio system is required to create a comfortable mobile computing environment. The reconfigurability of SDR is the answer to this problem.
The technical reason behind the popularity of the SDR concept is the development of reconfigurable devices for signal processing such as digital signal processors (DSP) and field programmable gate arrays (FPGA). The latest DSP""s operate at speeds up to 1.1 GHz and offer performance of nearly 9 billion instructions per second. FPGA""s can now provide densities of up to 2 million gates with low power consumption. These numbers are ever improving (refer to M. Cummings and S. Haruyama, xe2x80x9cFPGA in the Software Radio,xe2x80x9d IEEE Communications Magazine, vol.37, no.2, pp.108-112, February 1999, and F. J. Harris, xe2x80x9cConfigurable Logic for Digital Communications: Some Signal Processing Perspectivexe2x80x9d, IEEE Communications Magazine, vol.37, no.8, pp.107-111, August 1999).
Therefore, the real challenges facing SDR are the RF front-end, which is able to use the reconfigurability of the signal processing devices mentioned above and providing multimode and multiband communications.
In order to realize a multimode multiband SDR, the RF front-end should be able to support a wide range of frequencies and bandwidths. This task may be difficult with conventional RF front-end architectures (H. Tsurumi and Y. Suzuki, xe2x80x9cBroadband RF Stage Architecture for Software-Defined Radio in Handheld Terminal Applications,xe2x80x9d IEEE Communications Magazine, vol.37, no.2, pp.90-95, February 1999).
FIG. 1 is a block diagram of a conventional heterodyne receiver.
The heterodyne receiver 10 of FIG. 1 comprises a receiving antenna 11, a low noise amplifier (LNA) 12, a radio-frequency (RF) filter 13, an RF mixer 14, an RP use local oscillator 15, a first intermediate-frequency (IF) filter 16, an IF mixer 17, an IF use local oscillator 18, a second IF filter, an automatic gain controlled (AGC) amplifier 20, and an analog-to-digital converter (ADC) 21.
This architecture requires frequency-dependent passive components such as a dielectric filter 13 in the RF stage and surface acoustic wave (SAW) filter 16 in the first IF stage. A ceramic or crystal filter 19 is also needed in the second IF stage. The center frequencies and bandwidth of these filters 13, 14, and 19 are not flexible and not wide enough to support a multiband radio receiver.
Though switched capacitor filter banks and precision direct synthesis may be a choice to achieve wider bandwidths and programmability, they are not applicable to mobile terminals due to their size and weight.
Thus, the candidate for the RF front-end for SDR is the direct conversion (DC) principle.
FIG. 2 is a block diagram of a conventional direct conversion receiver.
The direct conversion receiver 30 of FIG. 2 comprises a receiving antenna 31, an LNA 32, RF mixers 33 and 34, an RP use local oscillator 35, a n/2 phase shifter 36, low-pass filters (LPF""s) 37 and 38, AGC amplifiers 39 and 40, and ADC""s 41 and 42.
In the direct conversion receiver 30 of FIG. 2, the received signal is down-converted directly to baseband by the quadrature mixer. The down-converted in-phase and quadrature (IQ) signals are prefiltered by the anti-aliasing LPF""s 37 and 38 with variable cutoff frequency. They are converted to digital signals by IQ ADC""s 41 and 42 and fed to the digital stage. The desired signal is selected by the software defined filter with programmable cutoff frequency.
The DC technique inherently has no image response, and the fixed-frequency image rejection filters can be eliminated. Furthermore, the anti-alias LPF can be designed with active, variable-bandwidth filters such as a switched capacitor embedded in an LSI chip.
In the conventional DC technique, the mixer has been used, however, in general it is difficult to design the mixer for a wide bandwidth. Therefore, if the conventional DC technique is applied to the software wireless system, improvement is necessary in point of widening the bandwidth.
Further, in the conventional direct conversion receiver, a sufficiently high local power is necessary in order to make the mixer operate with satisfactory characteristics. This invites an increases of power consumption of the receiver. Especially, when the carrier frequency is high, it is difficult to obtain a lower power consumption and a high local output power.
An object of the present invention is to provide a universal platform for software defined radio capable of solving the DC offset problem and supporting very wide bandwidths.
According to the first aspect of the present invention, there is provided a universal platform for software defined radio, comprising an n (n being an integer of 3 or more)-port receiver including: a first input terminal receiving as input a received signal, a second input terminal receiving as input a local signal, a generating means for generating two signals having a phase difference based on at least one signal between the received signal input from the first input terminal or the local signal input from the second input terminal and including at least one output terminal for outputting the generated signal, and at least one power detector for receiving as input the output signal from the output terminal and detecting the signal level of the input signal; and a converter for converting the output signal of the power detector to a plurality of signal components included in the received signal or the local signal.
According to a second aspect of the present invention, there is provided a universal platform for software defined radio, comprising an n (n being an integer of 3 or more)-port receiver including a first input terminal receiving as input a received signal, a second input terminal receiving as input a local signal, a generating means for generating two signals having a phase difference based on at least one signal between the received signal input from the first input terminal or the local signal input from the second input terminal and including at least one output terminal for outputting the generated signal, and at least one power detector for receiving as input the output signal from the output terminal and detecting the signal level of the input signal; at least one analog-to-digital (A/D) converter for converting the output analog signal from the corresponding power detector to a digital signal, and a digital signal processing part for converting the output signal of the power detector through the A/D converter to a plurality of signal components included in the received signal or the local signal.
In the present invention, the digital signal processing part compensates for the non-linearity of the power detector.
Further, in the present invention, the power detector preferably comprises a first field effect transistor receiving the input signal at its gate, a second field effect transistor with a source connected to a source of the first field effect transistor, a first gate bias supplying circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supplying circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a current source connected to the connecting point of the sources of the first field effect transistor and the second field effect transistor, a drain bias supplying circuit for supplying a drain bias voltage to the drains of the first field effect transistor and the second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and the reference potential, and wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is processed as a detection output.
Further, in the present invention, preferably, the first field effect transistor and the second field effect transistor have substantially the same characteristics, the drain bias supplying circuit includes a first drain bias use resistance element connected between the drain of the first field effect transistor and a voltage source and includes a second drain bias use resistance element connected between the drain of the second field effect transistor and a voltage source, a resistance of the first drain bias use resistance element and a resistance of the second drain bias use resistance element are set to substantially equivalent values, and a capacitance of the first capacitor and a capacitance of the second capacitor are set to substantially equivalent values.
Further, in the present invention, preferably, when a gate width of the first field effect transistor is Wga and a gate width of the second field effect transistor is Wgb, the ratio Wga/Wgb is set to N, the drain bias supplying circuit includes a first drain bias use resistance element connected between the drain of the first field effect transistor and a voltage source and includes a second drain bias use resistance element connected between the drain of the second field effect transistor and a voltage source, a resistance Ra of the first drain bias use resistance element and a resistance of the second drain bias use resistance Rb element are set so as to satisfy the condition Ra/Rb=1/N, and a capacitance of the first capacitor and a capacitance of the second capacitor are set to substantially equivalent values.
Further, in the present invention, the power detector preferably alternatively comprises a first field effect transistor receiving the input signal at its gate and with a source connected to a reference potential, a second field effect transistor with a source connected to the reference potential, a first gate bias supplying circuit for supplying a gate bias voltage to the gate of the first field effect transistor, a second gate bias supplying circuit for supplying a gate bias voltage to a gate of the second field effect transistor, a drain bias supplying circuit for supplying a drain bias voltage to the drains of the first field effect transistor and the second field effect transistor, a first capacitor connected between the drain of the first field effect transistor and a reference potential, and a second capacitor connected between the drain of the second field effect transistor and the reference potential, and wherein the voltage difference between the drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor is processed as a detection output.
According to the present invention, for example, an RF signal is received and input to the generating means of the n-port receiver through the first input terminal, while the local signal generated, for example, by a local oscillator is input to the generating means of the n-port receiver through the second input terminal.
In the generating means, two signals having a phase difference based on the received signal or the local signal are generated. The generated signal is output to the power detector from the output terminal (port).
In the power detector, the input signal level is detected. The detected signal is, for example, converted from an analog to digital format and fed to the digital signal processing part.
In the digital signal processing part, the converted digital signal of the power detector is converted to a plurality of signal components included in the received signal or the local signal.